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COA Unit Wise Question Bank-IMPORTANT (NOV-2019)-SPPU

Unit wise Question Bank (A.Y. 2019-20, Semester-I)
Subject:- Computer Organization and Architecture


 Unit No. – I 

Name of Unit: Computer Evolution And Performance


1 What are functional units? Discuss the basic functional units of a computer? 

2 With a neat diagram explain the basic operational concepts of computer? 

3 Explain IAS architecture with the help of neat diagram and list the instructions supported by IAS computer.

4 Draw instruction cycle state diagram and explain execution of instruction in detail. 

5 Explain various types of buses? 

6 Discuss the functions of system software? 

7 Discuss and differentiate multi computers and multi processors.

8 Explain the different types of data representation? 

9 Differentiate between combinational and sequential ALU. 

10 Using the booth’s algorithm multiply the following: Multiplicand: 13, Multiplier: -11 

11 Divide the following unsigned numbers using restoring division method Dividend= 1000, Divisor= 11 

12 Explain Booth’s algorithm to multiply the following pair of signed two’s complement numbers: A= 110011 multiplicand B= 101100 multiplier 

13 Perform the division on the following numbers using non- restoring division algorithm. Dividend= 1101, Divisor= 0100 

14 Represent (-309.1875) base 10 in single precision and double precision formats 

15 Draw the flowchart for floating point addition and explain. 

16 Represent 32.75 and 18.125 in single precision IEEE 754 representation. 

17 Give with the help of flowchart non-restoring division algorithm


Unit No. – II 
Name of Unit: Computer Memory System 


1 Explain the key characteristics of computer memory systems in detail. 

2 What is the use of cache memory? 

3 Explain cache coherence strategies.

4 Which techniques are used to perform the write operations in cache memory? 

5 Discuss any six ways of improving the cache performance. 

6 A block set associative cache consists of 64 blocks divided into 4 block sets. The main memory contains 4096 blocks, each consists of 128 words of 16 bits length: i) How many bits are there in main memory? ii) How many bits are there in each of the TAG, SET and WORD fields? 

7 Define the Static RAM (SRAM). Explain the working of SRAM cell with a neat diagram. 

8 Define the Dynamic RAM (DRAM). Explain the working of DRAM with a neat diagram. 

9 Define the Read Only Memory. Explain in detail the types of ROM’s. 

10 Define and discuss the types of replacement algorithms. 

11 Explain the following mapping functions: a) Associative mapping. b) Direct mapping. c) Set Associative mapping 

12 Explain the following secondary storage devices: a) Magnetic disk. b) Magnetic tape. 

13 Write note on RAID disk arrays.


Unit No. – III
Name of Unit: Input Output System 


1 Write a short note on external devices. 

2 Draw and explain generic model of computer showing OI/O module. 

3 What are the features of I/O modules. 

4 Compare memory mapped I/O and I/O mapped I/O. 

5 What are the different I/O commands? 

6 Explain interrupt driven I/O. 

7 Compare programmed I/O and interrupt driven I/O. 

8 Define interrupt latency. Enlist the steps involved in handling an interrupt request. 

9 Discuss the design issues to implement interrupt driven I/O. 

10 Explain the principles of multilevel interrupt system. 

11 Explain the action carried out by the processor after occurrence of an interrupt. 

12 List the features of 82C59A. 

13 Explain about asynchronous data transfer and asynchronous communication interface. 

14 Explain about interrupt priorities. 

15 Explain about DMA in detail. 

16 Explain in detail DMA data transfer modes. 

17 What is the use of DMA? What is cycle stealing in DMA? 

18 List the features of 8237 DMA controller. 

19 Explain the process of communication between a CPU and IOP. 

20 Write a short note on I/O processor. 

21 Draw and explain thunderbolt protocol architecture. 



Unit No. – IV Name of Unit: Instruction Set

1 Write a short note on external devices.

2 Draw and explain generic model of computer showing OI/O module. 

3 What are the features of I/O modules. 

4 Compare memory mapped I/O and I/O mapped I/O. 

5 What are the different I/O commands? 

6 Explain interrupt driven I/O. 

7 Compare programmed I/O and interrupt driven I/O. 

8 Define interrupt latency. Enlist the steps involved in handling an interrupt request. 

9 Discuss the design issues to implement interrupt driven I/O. 

10 Explain the principles of multilevel interrupt system. 

11 Explain the action carried out by the processor after occurrence of an interrupt. 

12 List the features of 82C59A. 

13 Explain about asynchronous data transfer and asynchronous communication interface. 

14 Explain about interrupt priorities. 

15 Explain about DMA in detail. 

16 Explain in detail DMA data transfer modes. 

17 What is the use of DMA? What is cycle stealing in DMA? 

18 List the features of 8237 DMA controller. 

19 Explain the process of communication between a CPU and IOP. 

20 Write a short note on I/O processor. 

21 Draw and explain thunderbolt protocol architecture.  


Unit No. – V Name of Unit: Processor Organization 

1 Draw and explain functional block diagram of 8086. 

2 List the features of 8086 microprocessor. 

3 State different sets of registers within the processor and explain their use. 

4 Draw and explain programmer’s model of 8086. 

5 Explain the instruction cycle. 

6 Draw the instruction cycle state diagram. 

7 What is Pipelining? 

8 What are the major characteristics of a Pipeline? 

9 What are the various stages in a Pipeline execution? 

10 What are the types of pipeline hazards? 

11 Define structural, data, and control hazard. 

12 List two conditions when processor can stall. 

13 List the types of data hazards. 

14 List the techniques used for overcoming hazard. 

15 What is instruction level parallelism? 

16 List the various pipelined processors. 

17 Why we need an instruction buffer in a pipelined CPU? 

18 What are the problems faced in instruction pipeline? 


 Unit No. – VI Name of Unit: Basic Processing Unit 

1 . Draw and explain typical hardware control unit. 

2 . Draw and explain about micro program control unit. 

3 . Explain in detail following micro instruction sequencing techniques: i) Single Address fields ii) Variable Address fields 

4 . Write short notes on (i)Micro instruction format (ii) Symbolic micro instruction 

5 . Explain multiple bus organization in detail. 

6 . How are the control signals generated in hardwired control unit? 

7 . What are the advantages of multiple bus organization over a single bus organization? 

8 . Write control sequencing for the executing the instruction. Add R4,R5,R6. 

9 . What are the types of micro instruction? 

10. Name the methods for generating the control signals. 

11. Draw and explain single bus organization of the CPU. 

12. Explain the sequence of operations needed to perform processor functions: i) Fetching a word from memory ii) Performing an arithmetic or logical operation 

13. Explain in detail state table design method for hardwired control. 

14. Explain the design of multiplier control unit using delay element method. 

15. For a single bus organization of CPU draw flowchart of a micro program for instruction : Add (Rsrc)+ R dest. 

16. Compare horizontal and vertical microinstruction representation. 

17. Compare superscalar and super pipelined approaches in superscalar processor.

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